// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
 *
 * Copyright (C) 2018 Synaptics Incorporated
 *
 * Author: Jisheng Zhang <jszhang@kernel.org>
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>

#include "sdhci-pltfm.h"

#define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)

/* DWCMSHC specific Mode Select value */
#define DWCMSHC_CTRL_HS400 0x7

#define DWCMSHC_VER_ID 0x500
#define DWCMSHC_VER_TYPE 0x504
#define DWCMSHC_HOST_CTRL3 0x508
#define DWCMSHC_EMMC_CONTROL 0x52c
#define DWCMSHC_EMMC_ATCTRL 0x540

/* Rockchip specific Registers */
#define DWCMSHC_EMMC_DLL_CTRL 0x800
#define DWCMSHC_EMMC_DLL_RXCLK 0x804
#define DWCMSHC_EMMC_DLL_TXCLK 0x808
#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
#define DWCMSHC_EMMC_DLL_STATUS0 0x840
#define DWCMSHC_EMMC_DLL_START BIT(0)
#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
#define DWCMSHC_EMMC_DLL_START_POINT 16
#define DWCMSHC_EMMC_DLL_INC 8
#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
#define DLL_RXCLK_NO_INVERTER 1
#define DLL_RXCLK_INVERTER 0
#define DWCMSHC_ENHANCED_STROBE BIT(8)
#define DLL_LOCK_WO_TMOUT(x)                                                                                           \
    ((((x)&DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && (((x)&DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
#define ROCKCHIP_MAX_CLKS 3

#define BOUNDARY_OK(addr, len) (((addr) | (SZ_128M - 1)) == (((addr) + (len)-1) | (SZ_128M - 1)))

struct dwcmshc_priv {
    struct clk *bus_clk;

    /* Rockchip specified optional clocks */
    struct clk_bulk_data rockchip_clks[ROCKCHIP_MAX_CLKS];
    int txclk_tapnum;
    unsigned int actual_clk;
};

/*
 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
 * so that each DMA transfer doesn't exceed the boundary.
 */
static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, unsigned int cmd)
{
    int tmplen, offset;

    if (likely(!len || BOUNDARY_OK(addr, len))) {
        sdhci_adma_write_desc(host, desc, addr, len, cmd);
        return;
    }

    offset = addr & (SZ_128M - 1);
    tmplen = SZ_128M - offset;
    sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);

    addr += tmplen;
    len -= tmplen;
    sdhci_adma_write_desc(host, desc, addr, len, cmd);
}

static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, struct mmc_request *mrq)
{
    struct sdhci_host *host = mmc_priv(mmc);

    /*
     * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
     * block count register which doesn't support stuff bits of
     * CMD23 argument on dwcmsch host controller.
     */
    if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) {
        host->flags &= ~SDHCI_AUTO_CMD23;
    } else {
        host->flags |= SDHCI_AUTO_CMD23;
    }
}

static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
    dwcmshc_check_auto_cmd23(mmc, mrq);

    sdhci_request(mmc, mrq);
}

static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
{
    u16 ctrl_2;

    ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
    /* Select Bus Speed Mode for host */
    ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
    if ((timing == MMC_TIMING_MMC_HS200) || (timing == MMC_TIMING_UHS_SDR104)) {
        ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
    } else if (timing == MMC_TIMING_UHS_SDR12) {
        ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
    } else if ((timing == MMC_TIMING_UHS_SDR25) || (timing == MMC_TIMING_MMC_HS)) {
        ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
    } else if (timing == MMC_TIMING_UHS_SDR50) {
        ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
    } else if ((timing == MMC_TIMING_UHS_DDR50) || (timing == MMC_TIMING_MMC_DDR52)) {
        ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
    } else if (timing == MMC_TIMING_MMC_HS400) {
        ctrl_2 |= DWCMSHC_CTRL_HS400;
    }
    sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}

static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
{
    u32 vendor;
    struct sdhci_host *host = mmc_priv(mmc);

    vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL);
    if (ios->enhanced_strobe) {
        vendor |= DWCMSHC_ENHANCED_STROBE;
    } else {
        vendor &= ~DWCMSHC_ENHANCED_STROBE;
    }

    sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL);
}

static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
{
    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
    struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
    u32 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, extra;
    int err;

    host->mmc->actual_clock = 0;

    if (clock == 0) {
        return;
    }

    /* Rockchip platform only support 375KHz for identify mode */
    if (clock <= 0x61a80) {
        clock = 0x5b8d8;
    }

    err = clk_set_rate(pltfm_host->clk, clock);
    if (err) {
        dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
    }

    sdhci_set_clock(host, clock);

    /* Disable cmd conflict check */
    extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
    extra &= ~BIT(0);
    sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);

    if (clock <= 0x3197500) {
        /* Disable DLL and reset both of sample and drive clock */
        sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
        sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
        sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
        return;
    }

    /* Reset DLL */
    sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
    udelay(1);
    sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);

    /*
     * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
     * we must set it in higher speed mode.
     */
    extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;

    sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);

    /* Init DLL settings */
    extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 0x2 << DWCMSHC_EMMC_DLL_INC | DWCMSHC_EMMC_DLL_START;
    sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
    err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, extra, DLL_LOCK_WO_TMOUT(extra), 1,
                             0x1f4 * USEC_PER_MSEC);
    if (err) {
        dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
        return;
    }

    extra = 0x1 << 0x10 | /* tune clock stop en */
            0x2 << 0x11 | /* pre-change delay */
            0x3 << 0x13;  /* post-change delay */
    sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL);

    if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
        txclk_tapnum = priv->txclk_tapnum;
    }

    extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_TXCLK_TAPNUM_FROM_SW | txclk_tapnum;
    sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);

    extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_STRBIN_TAPNUM_DEFAULT | DLL_STRBIN_TAPNUM_FROM_SW;
    sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
}

static const struct sdhci_ops sdhci_dwcmshc_ops = {
    .set_clock = sdhci_set_clock,
    .set_bus_width = sdhci_set_bus_width,
    .set_uhs_signaling = dwcmshc_set_uhs_signaling,
    .get_max_clock = sdhci_pltfm_clk_get_max_clock,
    .reset = sdhci_reset,
    .adma_write_desc = dwcmshc_adma_write_desc,
};

static const struct sdhci_ops sdhci_dwcmshc_rk_ops = {
    .set_clock = dwcmshc_rk_set_clock,
    .set_bus_width = sdhci_set_bus_width,
    .set_uhs_signaling = dwcmshc_set_uhs_signaling,
    .get_max_clock = sdhci_pltfm_clk_get_max_clock,
    .reset = sdhci_reset,
    .adma_write_desc = dwcmshc_adma_write_desc,
};

static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
    .ops = &sdhci_dwcmshc_ops,
    .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
    .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
};

static const struct sdhci_pltfm_data sdhci_dwcmshc_rk_pdata = {
    .ops = &sdhci_dwcmshc_rk_ops,
    .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
    .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
};

static int rockchip_pltf_init(struct sdhci_host *host, struct dwcmshc_priv *priv)
{
    int err;

    priv->rockchip_clks[0x0].id = "axi";
    priv->rockchip_clks[0x1].id = "block";
    priv->rockchip_clks[0x2].id = "timer";
    err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
    if (err) {
        dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
        return err;
    }

    err = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
    if (err) {
        dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
        return err;
    }

    if (of_property_read_u32(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", &priv->txclk_tapnum)) {
        priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
    }

    /* Disable cmd conflict check */
    sdhci_writel(host, 0x0, DWCMSHC_HOST_CTRL3);
    /* Reset previous settings */
    sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
    sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
    return 0;
}

static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
    {
        .compatible = "snps,dwcmshc-sdhci",
        .data = &sdhci_dwcmshc_pdata,
    },
    {
        .compatible = "rockchip,dwcmshc-sdhci",
        .data = &sdhci_dwcmshc_rk_pdata,
    },
    {},
};

static int dwcmshc_probe(struct platform_device *pdev)
{
    struct sdhci_pltfm_host *pltfm_host;
    struct sdhci_host *host;
    struct dwcmshc_priv *priv;
    const struct sdhci_pltfm_data *pltfm_data;
    int err;
    u32 extra;

    pltfm_data = of_device_get_match_data(&pdev->dev);
    if (!pltfm_data) {
        dev_err(&pdev->dev, "Error: No device match data found\n");
        return -ENODEV;
    }

    host = sdhci_pltfm_init(pdev, pltfm_data, sizeof(struct dwcmshc_priv));
    if (IS_ERR(host)) {
        return PTR_ERR(host);
    }

    /*
     * extra adma table cnt for cross 128M boundary handling.
     */
    extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
    if (extra > SDHCI_MAX_SEGS) {
        extra = SDHCI_MAX_SEGS;
    }
    host->adma_table_cnt += extra;

    pltfm_host = sdhci_priv(host);
    priv = sdhci_pltfm_priv(pltfm_host);

    pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
    if (IS_ERR(pltfm_host->clk)) {
        err = PTR_ERR(pltfm_host->clk);
        dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
        goto free_pltfm;
    }
    err = clk_prepare_enable(pltfm_host->clk);
    if (err) {
        goto free_pltfm;
    }

    priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
    if (!IS_ERR(priv->bus_clk)) {
        clk_prepare_enable(priv->bus_clk);
    }

    err = mmc_of_parse(host->mmc);
    if (err) {
        goto err_clk;
    }

    sdhci_get_of_property(pdev);

    host->mmc_host_ops.request = dwcmshc_request;
    host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;

    if (pltfm_data == &sdhci_dwcmshc_rk_pdata) {
        err = rockchip_pltf_init(host, priv);
        if (err) {
            goto err_clk;
        }
    }

    err = sdhci_add_host(host);
    if (err) {
        goto err_clk;
    }

    pm_runtime_get_noresume(&pdev->dev);
    pm_runtime_set_active(&pdev->dev);
    pm_runtime_enable(&pdev->dev);
    pm_runtime_set_autosuspend_delay(&pdev->dev, 0x32);
    pm_runtime_use_autosuspend(&pdev->dev);
    pm_runtime_put_autosuspend(&pdev->dev);

    return 0;

err_clk:
    clk_disable_unprepare(pltfm_host->clk);
    clk_disable_unprepare(priv->bus_clk);
    clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
free_pltfm:
    sdhci_pltfm_free(pdev);
    return err;
}

static int dwcmshc_remove(struct platform_device *pdev)
{
    struct sdhci_host *host = platform_get_drvdata(pdev);
    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
    struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);

    sdhci_remove_host(host, 0);

    clk_disable_unprepare(pltfm_host->clk);
    clk_disable_unprepare(priv->bus_clk);
    clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);

    sdhci_pltfm_free(pdev);

    return 0;
}

#ifdef CONFIG_PM_SLEEP
static int dwcmshc_suspend(struct device *dev)
{
    struct sdhci_host *host = dev_get_drvdata(dev);
    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
    struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
    int ret;

    ret = sdhci_suspend_host(host);
    if (ret) {
        return ret;
    }

    clk_disable_unprepare(pltfm_host->clk);
    if (!IS_ERR(priv->bus_clk)) {
        clk_disable_unprepare(priv->bus_clk);
    }

    clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
    return ret;
}

static int dwcmshc_resume(struct device *dev)
{
    struct sdhci_host *host = dev_get_drvdata(dev);
    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
    struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
    int ret;

    ret = clk_prepare_enable(pltfm_host->clk);
    if (ret) {
        return ret;
    }

    if (!IS_ERR(priv->bus_clk)) {
        ret = clk_prepare_enable(priv->bus_clk);
        if (ret) {
            return ret;
        }
    }

    ret = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
    if (ret) {
        return ret;
    }

    return sdhci_resume_host(host);
}

static int dwcmshc_runtime_suspend(struct device *dev)
{
    struct sdhci_host *host = dev_get_drvdata(dev);
    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
    struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);

    priv->actual_clk = host->mmc->actual_clock;
    sdhci_set_clock(host, 0);

    return 0;
}

static int dwcmshc_runtime_resume(struct device *dev)
{
    struct sdhci_host *host = dev_get_drvdata(dev);
    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
    struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);

    sdhci_set_clock(host, priv->actual_clk);

    return 0;
}
#endif

static const struct dev_pm_ops dwcmshc_pmops = {SET_SYSTEM_SLEEP_PM_OPS(
    dwcmshc_suspend, dwcmshc_resume) SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, dwcmshc_runtime_resume, NULL)};
MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);

static struct platform_driver sdhci_dwcmshc_driver = {
    .driver =
        {
            .name = "sdhci-dwcmshc",
            .probe_type = PROBE_PREFER_ASYNCHRONOUS,
            .of_match_table = sdhci_dwcmshc_dt_ids,
            .pm = &dwcmshc_pmops,
        },
    .probe = dwcmshc_probe,
    .remove = dwcmshc_remove,
};
module_platform_driver(sdhci_dwcmshc_driver);

MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
MODULE_LICENSE("GPL v2");
